Meine ersten Funktionen sahen nicht viel anders aus, als ich mit dem I2C Bus angefangen habe:
Code:
/******************************************************************************/
/* tested OKAY */
/* wait max 5 ms that the SI bit in the I2C0CONSET Register becomes High */
/* return TRUE if Bit is or goes High in this time */
/* return FALSE if SI Bit never set in this time */
/* normaly after clearing the SI bit in the I2CCONSET register, the */
/* shift transfer startet. 9 clock cycles, 8 data, 1 acknowlwdge. if all */
/* bits shifted out and the Ackbit received the SI bit sets automatically by */
/* the hardware. */
/* shift clock is 100Khz = 10us per bit * 9 = 90 usec. */
/* timeout was set to 5ms */
/* !!!! after a stop condition, this bit is alwas zero and never set. */
/* info: the SystemTickCount increments every milli second TIMER0 Interrupt */
BOOL wait_i2c_SI()
{ U32 time;
time = SystemTickCount + 2; /* 07.11.2011 wait max 2 ms (timeout) */
do
{
if (LPC_I2C0CONSET & I2CONSET_SI) /* if SI bit is set */
return TRUE; /* return with TRUE */
} while (SystemTickCount < time); /* else wait */
/* if the above lines are interrupted, maybe an timout occure */
/* so we test the SI flag again, after timeout */
if (LPC_I2C0CONSET & I2CONSET_SI) /* if SI bit is set after timeout */
return TRUE; /* return with TRUE */
return FALSE; /* else time out return FALSE */
}
/******************************************************************************/
BOOL ee_read(U32 EE_Address,
void *DataAddress,
U32 DataSize)
{ U32 time;
volatile U8* dataptr = DataAddress;
/* the EEPROM write cycle time is max 20ms for byte and page write */
/* maybe we must wait, because the last write is not ready now */
/* other interrupts may occur, so we set the max waittime to 100ms */
time = SystemTickCount + EE_WRITE_CYCLE_TIME; /* set max waittime to 100 ms*/
while (ee_busy(EE_Address))
{
if ((SystemTickCount > time) && (ee_busy(EE_Address)))
return FALSE; /* EE BUSY Time Out Error */
}
LPC_I2C0CONSET = I2CONSET_STA; /* Set Start flag */
if (!wait_i2c_SI()) return FALSE; /* wait until SI Flag is set */
LPC_I2C0CONCLR = I2CONCLR_STAC; /* Clear the Start flag */
LPC_I2C0DAT = EE_SLAVE_ADDRESS | ((EE_Address >> 8) << 1); /* send Slave Address and the 3 Upper Adressbits */
LPC_I2C0CONCLR = I2CONCLR_SIC; /* clear the SI Flag */
/* starts the shift out Device Address */
if (!wait_i2c_SI()) return FALSE; /* wait until SI Flag is set */
LPC_I2C0DAT = (U8)(EE_Address); /* EEPROM Address */
LPC_I2C0CONCLR = I2CONCLR_SIC; /* clear the SI Flag */
/* starts the shift out EEPORM Address */
if (!wait_i2c_SI()) return FALSE; /* wait until SI Flag is set */
/* reading: first set the control byte (Slave Address) with RD bit=1 */
/* include the 3 Upper Adressbits from the eeprom address */
LPC_I2C0CONSET = I2CONSET_STA; /* Set Start flag, repeated start condition */
LPC_I2C0CONCLR = I2CONCLR_SIC; /* clear the SI Flag, start shift out repeatetd start condition */
if (!wait_i2c_SI()) return FALSE; /* wait until SI Flag is set */
LPC_I2C0CONCLR = I2CONCLR_STAC; /* Clear the Start flag */
LPC_I2C0DAT = EE_SLAVE_ADDRESS | ((EE_Address >> 8) << 1) | I2C_RD_BIT;
LPC_I2C0CONCLR = I2CONCLR_SIC; /* clear the SI Flag */
/* starts the shift out the control byte with RD Bit=1*/
if (!wait_i2c_SI()) return FALSE; /* wait until SI Flag is set */
LPC_I2C0CONSET = I2CONSET_AA; /* assert ACK after every received data byte */
/* start READ LOOP: */
while (DataSize--) /* read all data bytes from EEPROM with always ACK */
{
/* after the last byte the master must send "NACK" to end the sequential read 02.03.2011 */
if (!DataSize) LPC_I2C0CONCLR = I2CONSET_AA; /* assert NACK after last byte received 02.03.2011 */
LPC_I2C0CONCLR = I2CONCLR_SIC; /* clear the SI Flag */
/* starts the shift in data byte */
if (!wait_i2c_SI()) return FALSE; /* wait until SI Flag is set */
*dataptr++ = LPC_I2C0DAT; /* save received data byte */
}
/* end READ LOOP */
LPC_I2C0CONSET = I2CONSET_STO; /* set STOP condition, sets SDA-Pin to Low NOW */
LPC_I2C0CONCLR = I2CONCLR_SIC; /* clear the SI Flag */
/* starts the shift out STOP Condition */
/* clears the STOP bit */
/* !!!!!!! SI are never set , dont wait here */
return TRUE;
}
2011 habe ich anscheinend das neue EEPROM benutzt und merkte, dass ich ein NACK beim letzten Byte brauche....
Das war/ist ein CAT24C08 EEPROM
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