[VHDL] Globale Variable/Signal?

[redraven]

Fehler: Nonresolved signal 'z_alt' has multiple sources.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY auswahl IS
   PORT( 
      rst            : IN     std_logic;
      start          : IN     std_logic;
      zw_zeit        : IN     std_logic;
      enable_zaehler : OUT    std_logic;
      in_w_en        : OUT    std_logic;
      up_dn_zahler   : OUT    std_logic
   );

-- Declarations

END auswahl ;

--
ARCHITECTURE verh_auswahl OF auswahl IS

signal zw_z: std_logic := '0';
signal z_alt: integer := 1;

BEGIN  
  --Taster Reset Prozess
  
    reset_proc: process(rst)
  begin
    if rising_edge (rst) then
      enable_zaehler <= '0';
      in_w_en <= '0';
      up_dn_zahler <= '1';
      zw_z <= '0';
      z_alt <= 1;
    end if;
  end process;
  
  --Taster Zwischenzeit Prozess
  
  zw_zeit_proc: process(zw_zeit)
  begin
    if rising_edge (zw_zeit) then
      if zw_z = '0' then
        zw_z <= '1';
        in_w_en <= '1';
      else
        in_w_en <= '0';
      end if;
    end if;
  end process;
  
  --Enable-Zähler-Signal Prozess
  
  run_proc: process(start)
    begin
      if rising_edge(start) then
        if zw_z = '0' then        
          if z_alt = 1 then
            enable_zaehler <= '1';
            up_dn_zahler <= '1';
            z_alt <= 2;
          elsif z_alt = 2 then
            enable_zaehler <= '0';
            z_alt <= 3;
          elsif z_alt = 3 then
            enable_zaehler <= '1';
            up_dn_zahler <= '0';
            z_alt <= 4;
          else
            enable_zaehler <= '0';
            z_alt <= 1;
          end if;
        end if;
      end if;
    end process;

END ARCHITECTURE verh_auswahl;