#pragma config FOSC = IRC //POR => Internal RC oscillator.
#pragma config PLLEN = OFF //PLL is Software Controlled.
#pragma config CPUDIV = NOCLKDIV //No CPU System Clock divide.
#pragma config HFOFST = OFF //Warten bis System-clock stabil.
#pragma config PCLKEN = OFF //Primary clock is under software control.
#pragma config FCMEN = OFF //Fail-Safe Clock Monitor disabled.
#pragma config PWRTEN = ON //Power-UP-Timer enabled.
#pragma config MCLRE = ON //MCLR pin enabled, RA3 input pin disabled.
#pragma config BOREN = OFF //Brown-out Reset disabled.
#pragma config IESO = OFF //Oscillator Switchover mode disabled.
#pragma config LVP = OFF //Low Voltage ICSP.
#pragma config STVREN = OFF //Stack full/underflow will not cause Reset.
#pragma config WDTEN = OFF //Watchdog Timer OFF.
#pragma config BBSIZ = OFF //1kW boot block size.
#pragma config EBTR0 = OFF //Block 0 not prot. from table reads exec. in other blocks.
#pragma config EBTR1 = OFF //Block 1 not prot. from table reads exec. in other blocks.
#pragma config EBTRB = OFF //Boot block not prot. from table reads exec. in other blocks.
#pragma config WRT0 = OFF //Block 0 not write-protected.
#pragma config WRT1 = OFF //Block 1 not write-protected.
#pragma config WRTB = OFF //Boot block not write-protected.
#pragma config WRTC = OFF //Configuration registers not write-protected.
#pragma config WRTD = OFF //Data EEPROM not write-protected.
#pragma config CP0 = OFF //Block 0 not code-protected.
#pragma config CP1 = OFF //Block 1 not code-protected.
#pragma config CPB = OFF //Boot block not code-protected.
#pragma config CPD = OFF //Data EEPROM not code-protected.
#pragma config XINST = OFF //Instruction set extension & Indexed Addr. mode disabled.
OSCCONbits.IRCF0 = 1; //16 MHz (Eigentlich unnötig, da 8MHz standard.)
OSCCONbits.IRCF1 = 1;
OSCCONbits.IRCF2 = 1;
OSCTUNEbits.SPLLEN = 1; //PLL: Enable
OSCCONbits.SCS0 = 0; //Switch => 0: PLL; 0: Primary Quarz.
OSCCONbits.SCS1 = 0; //Switch => 0: PLL; 0: Primary Quarz.
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