Ok danke für die schnelle Antwort. Also das heißt ich könnte auch die Daten ausgeben bevor ich schon mit dem /CS auf low gehe oder? und wenn dann /CS und /WR auf low gehen sind die Daten bzw die Adresse schon verfügbar??
Hier mal der gesamte Code
Code:
#define F_CPU 4000000UL /* 16 MHz CPU clock */
#include <util/delay.h>
#include <avr/io.h>
#include "ethernet.h"
void init_ports() {
WIZ_CONFIG_DDR = 0xBF;
ADDRESS_L_DDR = 0xFF;
ADDRESS_H_DDR = 0xFF;
DATA_L_DDR = 0xFF;
WIZ_CONFIG =0xBF;
}
void init_wiznet() {
// Hardware reset
WIZ_CONFIG |= RESET;
_delay_us(10);
WIZ_CONFIG &= ~RESET;
_delay_us(10);
WIZ_CONFIG |= RESET;
_delay_ms(20);
// register reset
write_data_wiznet(MR0, 0x80);
write_data_wiznet(MR1, 0x00);
//Set gateway IP address
/* write_data_wiznet(GAR0, 192);
write_data_wiznet(GAR1, 168);
write_data_wiznet(GAR2, 0);
write_data_wiznet(GAR3, 1);
*/
//Set Subnet mask
write_data_wiznet(SUBR0, 255);
write_data_wiznet(SUBR1, 255);
write_data_wiznet(SUBR2, 255);
write_data_wiznet(SUBR3, 0);
//Set MAC address
write_data_wiznet(SHAR0, 0x00);
write_data_wiznet(SHAR1, 0xC0);
write_data_wiznet(SHAR2, 0x9F);
write_data_wiznet(SHAR3, 0x9E);
write_data_wiznet(SHAR4, 0x80);
write_data_wiznet(SHAR5, 0x2F);
//Set own IP address
write_data_wiznet(SIPR0, 192);
write_data_wiznet(SIPR1, 168);
write_data_wiznet(SIPR2, 0);
write_data_wiznet(SIPR3, 73);
//Allocation internal TX/RX memory for SOCKETn
}
void write_data_wiznet(int registers, int value) {
DATA_L_DDR = 0xFF; //setting as outputs
_delay_ms(5);
ADDRESS_H = getHighAddress(registers);
ADDRESS_L = getLowAddress(registers);
_delay_us(1);
WIZ_CONFIG &= ~CS; // CS low setzen -> Wiznet enabled
//WIZ_CONFIG |= RD; // RD high setzen -> read disabled
_delay_us(1);
WIZ_CONFIG &= ~WR; // WR low setzen -> write enabled
_delay_us(0.010);
DATA_L = value;
_delay_us(1);
WIZ_CONFIG |= WR; // WR high setzen -> write disabled
_delay_us(1);
WIZ_CONFIG |= CS; // CS high setzen -> Wiznet disabled
_delay_us(1);
ADDRESS_H = 0x00;
ADDRESS_L = 0x00;
DATA_L = 0x00;
}
int read_data_wiznet(int registers) {
int value = 0;
DATA_L_DDR = 0x00; //setting as inputs
WIZ_CONFIG &= ~CS; // CS low setzen -> Wiznet enabled
WIZ_CONFIG &= ~RD; // RD low setzen -> read enabled
WIZ_CONFIG |= WR; // WR high setzen -> write disabled
ADDRESS_H |= getHighAddress(registers);
ADDRESS_L = getLowAddress(registers);
value = DATA_L;
WIZ_CONFIG |= CS; // CS high setzen -> Wiznet disabled
return value;
}
int getHighAddress(int address) {
int address_h = 0;
address_h = (address & 0xFF00) >> 8;
return address_h;
}
int getLowAddress(int address) {
int address_l = 0;
address_l = (address & 0x00FF);
return address_l;
}
//ethernet.h
#define WIZ_CONFIG PORTD
#define WIZ_CONFIG_DDR DDRD
#define RD _BV(PD2)
#define CS _BV(PD3)
#define RESET _BV(PD4)
#define WR _BV(PD5)
#define DATA_L PORTA
#define DATA_L_DDR DDRA
#define ADDRESS_L PORTC
#define ADDRESS_H PORTB
#define ADDRESS_L_DDR DDRC
#define ADDRESS_H_DDR DDRB
//mode register
#define MR0 0x0000
#define MR1 0x0001
// register: Gateway address
#define GAR0 0x0010
#define GAR1 0x0011
#define GAR2 0x0012
#define GAR3 0x0013
// register: Subnet mask
#define SUBR0 0x0014
#define SUBR1 0x0015
#define SUBR2 0x0016
#define SUBR3 0x0017
// register: Hardware address
#define SHAR0 0x0008
#define SHAR1 0x0009
#define SHAR2 0x000A
#define SHAR3 0x000B
#define SHAR4 0x000C
#define SHAR5 0x000D
// register: IP address
#define SIPR0 0x0018
#define SIPR1 0x0019
#define SIPR2 0x001A
#define SIPR3 0x001B
// register: Sockets
#define TMSR0 0x0020
#define TMSR1 0x0021
#define RMSR0 0x0028
#define RMSR1 0x0029
#define MTYPER0 0x0030
#define MTYPER1 0x0031
void init_ports();
int getHighAddress(int address);
int getLowAddress(int address);
void write_data_wiznet(int registers, int value);
int read_data_wiznet(int registers);
void init_wiznet();
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