32 bits general purpose asynchronous bus architecture up to 33Mhz for easy system application
• Single chip solution integrating 10/100 TP transceiver to reduce overall cost
• Optional MII interface for external tranceiver.
• Fully compliant with the IEEE 802.3u spec. • Supports 32/16 bits x1, x2, x4 burst read transfers for the receive packet buffer
• Packet buffer access through an IO mapped port or host DMA for a wide variety of bus applications
• Programmable bus integrity check timer and interrupt assertion scheme
• Supports 16/8 bits packet buffer data width and 32/ 16 bits host bus data width • Separated TX and RX FIFOs to support the full du- plex mode, independent TX and RX channel • Rich on-chip registers to support a wide variety of network management functions • 32 bits general purpose asynchronous bus architecture up to 33Mhz for easy system application • Single chip solution integrating 10/100 TP transceiver to reduce overall cost • Optional MII interface for external tranceiver. • Fully compliant with the IEEE 802.3u spec. • Supports 32/16 bits x1, x2, x4 burst read transfers for the receive packet buffer • Packet buffer access through an IO mapped port or host DMA for a wide variety of bus applications • Programmable bus integrity check timer and interrupt assertion scheme • Supports 16/8 bits packet buffer data width and 32/ 16 bits host bus data width • Separated TX and RX FIFOs to support the full du- plex mode, independent TX and RX channel • Rich on-chip registers to support a wide variety of network management functions
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