So hab was gefunden. Ich poste das hier nochmal just for info, falls jemand anderes nochmal auf den Fehler stößt:

Hi List,
On the issue of INT0 on the Mega32 (and several others), I spernt a few
minutes looking at the data sheets So far as ATMEL is conserned, INT0 and
INT1 CAN be configured for Low, Any Change, Falling, or Rising. It is INT2
that only triggers on Low Level (probably because they had no more bits to
control it). Mark must have misread this or typo'd it when he added the
newer Megas.

The upshot is:
There IS a compiler error. It states that INTO - INT2 only trigger on low
level.
There is also, I believe, a related error in the simulator that keeps M8,
M16, M32, & M64 from responding to INT0 but allows the other Megas to act
properly.

Workaround? YES, for the compiler... and it's simple.
In the MCUCR (Recognized by Bascom so you can talk to it)
Bits .0 and .1 control INT0
Bits .2 and .3 control INT1
The Bit patterns to set up either Interrupt are:
00 Low Level
01 Any Change* (A NICE Feature not yet addressed by Bascom)
10 Falling Edge
11 Rising Edge
(Each bit has its own name, but these names weren't known to Bascom,)
Simpler code is possible and assembler would be more compact, but the
following code does it:

' To Configure INT0 = FALLING and conserve MCUCR
MCUCR = MCUCR AND &HFC 'Mask off Bits .0 and .1
MCUCR = MCUCR OR &H02 ' "Fallimg" bit pattern

That's all there is. Move two bits to the left for INT1.
DISCLAIMER:
I tested this in the simulator only, not on hardware. It works fine on all
but the mega's listed above. I ASSUME that a simulator error prevents
proper INT action in the simulator and that the workaround will make the
hardware respond properly. I'd appreciate hearing if it does.

P.S.
Its amazing what these data sheets can tell you.

JWC

*On most or all of newer AVRs.