@oberallgeier
Ich hab schon mal eine Header Datei auf den neuen Controller angepasst. War ne echte Fleissaufgabe.
Ich hab die iom328pb.h mal als Code hier eingestellt.
Ich hab bis jetzt immer mit CodeVision AVR gearbeitet und bin deshalb mit AVR-GCC noch nicht so vertraut.
/* Copyright (c) 2007 Atmel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*/
/* $Id: iom328pb.h,v 1.3.2.14 2009/02/11 18:05:28 arcanum Exp $ */
/* avr/iom328pb.h - definitions for ATmega328Pb. */
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "iom328pb.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
#ifndef _AVR_IOM328PB_H_
#define _AVR_IOM328PB_H_ 1
/* Registers and associated bit numbers */
#define PINB _SFR_IO8(0x03)
#define PINB0 0
#define PINB1 1
#define PINB2 2
#define PINB3 3
#define PINB4 4
#define PINB5 5
#define PINB6 6
#define PINB7 7
#define DDRB _SFR_IO8(0x04)
#define DDB0 0
#define DDB1 1
#define DDB2 2
#define DDB3 3
#define DDB4 4
#define DDB5 5
#define DDB6 6
#define DDB7 7
#define PORTB _SFR_IO8(0x05)
#define PORTB0 0
#define PORTB1 1
#define PORTB2 2
#define PORTB3 3
#define PORTB4 4
#define PORTB5 5
#define PORTB6 6
#define PORTB7 7
#define PINC _SFR_IO8(0x06)
#define PINC0 0
#define PINC1 1
#define PINC2 2
#define PINC3 3
#define PINC4 4
#define PINC5 5
#define PINC6 6
#define DDRC _SFR_IO8(0x07)
#define DDC0 0
#define DDC1 1
#define DDC2 2
#define DDC3 3
#define DDC4 4
#define DDC5 5
#define DDC6 6
#define PORTC _SFR_IO8(0x08)
#define PORTC0 0
#define PORTC1 1
#define PORTC2 2
#define PORTC3 3
#define PORTC4 4
#define PORTC5 5
#define PORTC6 6
#define PIND _SFR_IO8(0x09)
#define PIND0 0
#define PIND1 1
#define PIND2 2
#define PIND3 3
#define PIND4 4
#define PIND5 5
#define PIND6 6
#define PIND7 7
#define DDRD _SFR_IO8(0x0A)
#define DDD0 0
#define DDD1 1
#define DDD2 2
#define DDD3 3
#define DDD4 4
#define DDD5 5
#define DDD6 6
#define DDD7 7
#define PORTD _SFR_IO8(0x0B)
#define PORTD0 0
#define PORTD1 1
#define PORTD2 2
#define PORTD3 3
#define PORTD4 4
#define PORTD5 5
#define PORTD6 6
#define PORTD7 7
#define PINE _SFR_IO8(0x0C)
#define PINE0 0
#define PINE1 1
#define PINE2 2
#define PINE3 3
#define PINE4 4
#define PINE5 5
#define PINE6 6
#define PINE7 7
#define DDRE _SFR_IO8(0x0D)
#define DDE0 0
#define DDE1 1
#define DDE2 2
#define DDE3 3
#define DDE4 4
#define DDE5 5
#define DDE6 6
#define DDE7 7
#define PORTE _SFR_IO8(0x0E)
#define PORTE0 0
#define PORTE1 1
#define PORTE2 2
#define PORTE3 3
#define PORTE4 4
#define PORTE5 5
#define PORTE6 6
#define PORTE7 7
#define TIFR0 _SFR_IO8(0x15)
#define TOV0 0
#define OCF0A 1
#define OCF0B 2
#define TIFR1 _SFR_IO8(0x16)
#define TOV1 0
#define OCF1A 1
#define OCF1B 2
#define ICF1 5
#define TIFR2 _SFR_IO8(0x17)
#define TOV2 0
#define OCF2A 1
#define OCF2B 2
#define TIFR3 _SFR_IO8(0x18)
#define TOV3 0
#define OCF3A 1
#define OCF3B 2
#define ICF3 5
#define TIFR4 _SFR_IO8(0x19)
#define TOV4 0
#define OCF4A 1
#define OCF4B 2
#define ICF4 5
#define PCIFR _SFR_IO8(0x1B)
#define PCIF0 0
#define PCIF1 1
#define PCIF2 2
#define PCIF3 3
#define EIFR _SFR_IO8(0x1C)
#define INTF0 0
#define INTF1 1
#define EIMSK _SFR_IO8(0x1D)
#define INT0 0
#define INT1 1
#define GPIOR0 _SFR_IO8(0x1E)
#define GPIOR00 0
#define GPIOR01 1
#define GPIOR02 2
#define GPIOR03 3
#define GPIOR04 4
#define GPIOR05 5
#define GPIOR06 6
#define GPIOR07 7
#define EECR _SFR_IO8(0x1F)
#define EERE 0
#define EEPE 1
#define EEMPE 2
#define EERIE 3
#define EEPM0 4
#define EEPM1 5
#define EEDR _SFR_IO8(0x20)
#define EEDR0 0
#define EEDR1 1
#define EEDR2 2
#define EEDR3 3
#define EEDR4 4
#define EEDR5 5
#define EEDR6 6
#define EEDR7 7
#define EEAR _SFR_IO16(0x21)
#define EEARL _SFR_IO8(0x21)
#define EEAR0 0
#define EEAR1 1
#define EEAR2 2
#define EEAR3 3
#define EEAR4 4
#define EEAR5 5
#define EEAR6 6
#define EEAR7 7
#define EEARH _SFR_IO8(0x22)
#define EEAR8 0
#define EEAR9 1
#define EEAR10 2
#define EEAR11 3
#define _EEPROM_REG_LOCATIONS_ 1F2021
#define GTCCR _SFR_IO8(0x23)
#define PSRSYNC 0
#define PSRASY 1
#define TSM 7
#define TCCR0A _SFR_IO8(0x24)
#define WGM00 0
#define WGM01 1
#define COM0B0 4
#define COM0B1 5
#define COM0A0 6
#define COM0A1 7
#define TCCR0B _SFR_IO8(0x25)
#define CS00 0
#define CS01 1
#define CS02 2
#define WGM02 3
#define FOC0B 6
#define FOC0A 7
#define TCNT0 _SFR_IO8(0x26)
#define TCNT0_0 0
#define TCNT0_1 1
#define TCNT0_2 2
#define TCNT0_3 3
#define TCNT0_4 4
#define TCNT0_5 5
#define TCNT0_6 6
#define TCNT0_7 7
#define OCR0A _SFR_IO8(0x27)
#define OCR0A_0 0
#define OCR0A_1 1
#define OCR0A_2 2
#define OCR0A_3 3
#define OCR0A_4 4
#define OCR0A_5 5
#define OCR0A_6 6
#define OCR0A_7 7
#define OCR0B _SFR_IO8(0x28)
#define OCR0B_0 0
#define OCR0B_1 1
#define OCR0B_2 2
#define OCR0B_3 3
#define OCR0B_4 4
#define OCR0B_5 5
#define OCR0B_6 6
#define OCR0B_7 7
#define GPIOR1 _SFR_IO8(0x2A)
#define GPIOR10 0
#define GPIOR11 1
#define GPIOR12 2
#define GPIOR13 3
#define GPIOR14 4
#define GPIOR15 5
#define GPIOR16 6
#define GPIOR17 7
#define GPIOR2 _SFR_IO8(0x2B)
#define GPIOR20 0
#define GPIOR21 1
#define GPIOR22 2
#define GPIOR23 3
#define GPIOR24 4
#define GPIOR25 5
#define GPIOR26 6
#define GPIOR27 7
#define SPCR0 _SFR_IO8(0x2C)
#define SPR00 0
#define SPR01 1
#define CPHA0 2
#define CPOL0 3
#define MSTR0 4
#define DORD0 5
#define SPE0 6
#define SPIE0 7
#define SPSR0 _SFR_IO8(0x2D)
#define SPI02X 0
#define WCOL0 6
#define SPIF0 7
#define SPDR0 _SFR_IO8(0x2E)
#define SPDR00 0
#define SPDR01 1
#define SPDR02 2
#define SPDR03 3
#define SPDR04 4
#define SPDR05 5
#define SPDR06 6
#define SPDR07 7
#define ACSRB _SFR_IO9(0x2F)
#define ACOE 0
#define ACSR _SFR_IO8(0x30)
#define ACIS0 0
#define ACIS1 1
#define ACIC 2
#define ACIE 3
#define ACI 4
#define ACO 5
#define ACBG 6
#define ACD 7
#define DWDR _SFR_IO8(0x31)
#define DWDR0 0
#define DWDR1 1
#define DWDR2 2
#define DWDR3 3
#define DWDR4 4
#define DWDR5 5
#define DWDR6 6
#define DWDR7 7
#define SMCR _SFR_IO8(0x33)
#define SE 0
#define SM0 1
#define SM1 2
#define SM2 3
#define MCUSR _SFR_IO8(0x34)
#define PORF 0
#define EXTRF 1
#define BORF 2
#define WDRF 3
#define MCUCR _SFR_IO8(0x35)
#define IVCE 0
#define IVSEL 1
#define PUD 4
#define BODSE 5
#define BODS 6
#define SPMCSR _SFR_IO8(0x37)
#define SELFPRGEN 0
#define PGERS 1
#define PGWRT 2
#define BLBSET 3
#define RWWSRE 4
#define RWWSB 6
#define SPMIE 7
#define WDTCSR _SFR_MEM8(0x60)
#define WDP0 0
#define WDP1 1
#define WDP2 2
#define WDE 3
#define WDCE 4
#define WDP3 5
#define WDIE 6
#define WDIF 7
#define CLKPR _SFR_MEM8(0x61)
#define CLKPS0 0
#define CLKPS1 1
#define CLKPS2 2
#define CLKPS3 3
#define CLKPCE 7
#define XFDCSR _SFR_MEM8(0x62)
#define XFDIE 0
#define XFDIF 1
#define PRR0 _SFR_MEM8(0x64)
#define PRADC 0
#define PRUSART0 1
#define PRSPI0 2
#define PRTIM1 3
#define PRUSART1 4
#define PRTIM0 5
#define PRTIM2 6
#define PRTWI0 7
#define OSCCAL _SFR_MEM8(0x66)
#define CAL0 0
#define CAL1 1
#define CAL2 2
#define CAL3 3
#define CAL4 4
#define CAL5 5
#define CAL6 6
#define CAL7 7
#define PCICR _SFR_MEM8(0x68)
#define PCIE0 0
#define PCIE1 1
#define PCIE2 2
#define PCIE3 3
#define EICRA _SFR_MEM8(0x69)
#define ISC00 0
#define ISC01 1
#define ISC10 2
#define ISC11 3
#define PCMSK0 _SFR_MEM8(0x6B)
#define PCINT0 0
#define PCINT1 1
#define PCINT2 2
#define PCINT3 3
#define PCINT4 4
#define PCINT5 5
#define PCINT6 6
#define PCINT7 7
#define PCMSK1 _SFR_MEM8(0x6C)
#define PCINT8 0
#define PCINT9 1
#define PCINT10 2
#define PCINT11 3
#define PCINT12 4
#define PCINT13 5
#define PCINT14 6
#define PCMSK2 _SFR_MEM8(0x6D)
#define PCINT16 0
#define PCINT17 1
#define PCINT18 2
#define PCINT19 3
#define PCINT20 4
#define PCINT21 5
#define PCINT22 6
#define PCINT23 7
#define TIMSK0 _SFR_MEM8(0x6E)
#define TOIE0 0
#define OCIE0A 1
#define OCIE0B 2
#define TIMSK1 _SFR_MEM8(0x6F)
#define TOIE1 0
#define OCIE1A 1
#define OCIE1B 2
#define ICIE1 5
#define TIMSK2 _SFR_MEM8(0x70)
#define TOIE2 0
#define OCIE2A 1
#define OCIE2B 2
#define TIMSK3 _SFR_MEM8(0x71)
#define TOIE3 0
#define OCIE3A 1
#define OCIE3B 2
#define ICIE3 5
#define TIMSK4 _SFR_MEM8(0x72)
#define TOIE4 0
#define OCIE4A 1
#define OCIE4B 2
#define ICIE4 5
#define PCMSK3 _SFR_MEM8(0x73)
#define PCINT24 0
#define PCINT25 1
#define PCINT26 2
#define PCINT27 3
#ifndef __ASSEMBLER__
#define ADC _SFR_MEM16(0x78)
#endif
#define ADCW _SFR_MEM16(0x78)
#define ADCL _SFR_MEM8(0x78)
#define ADCL0 0
#define ADCL1 1
#define ADCL2 2
#define ADCL3 3
#define ADCL4 4
#define ADCL5 5
#define ADCL6 6
#define ADCL7 7
#define ADCH _SFR_MEM8(0x79)
#define ADCH0 0
#define ADCH1 1
#define ADCH2 2
#define ADCH3 3
#define ADCH4 4
#define ADCH5 5
#define ADCH6 6
#define ADCH7 7
#define ADCSRA _SFR_MEM8(0x7A)
#define ADPS0 0
#define ADPS1 1
#define ADPS2 2
#define ADIE 3
#define ADIF 4
#define ADATE 5
#define ADSC 6
#define ADEN 7
#define ADCSRB _SFR_MEM8(0x7B)
#define ADTS0 0
#define ADTS1 1
#define ADTS2 2
#define ACME 6
#define ADMUX _SFR_MEM8(0x7C)
#define MUX0 0
#define MUX1 1
#define MUX2 2
#define MUX3 3
#define ADLAR 5
#define REFS0 6
#define REFS1 7
#define DIDR0 _SFR_MEM8(0x7E)
#define ADC0D 0
#define ADC1D 1
#define ADC2D 2
#define ADC3D 3
#define ADC4D 4
#define ADC5D 5
#define ADC6D 6
#define ADC7D 7
#define DIDR1 _SFR_MEM8(0x7F)
#define AIN0D 0
#define AIN1D 1
#define TCCR1A _SFR_MEM8(0x80)
#define WGM10 0
#define WGM11 1
#define COM1B0 4
#define COM1B1 5
#define COM1A0 6
#define COM1A1 7
#define TCCR1B _SFR_MEM8(0x81)
#define CS10 0
#define CS11 1
#define CS12 2
#define WGM12 3
#define WGM13 4
#define ICES1 6
#define ICNC1 7
#define TCCR1C _SFR_MEM8(0x82)
#define FOC1B 6
#define FOC1A 7
#define TCNT1 _SFR_MEM16(0x84)
#define TCNT1L _SFR_MEM8(0x84)
#define TCNT1L0 0
#define TCNT1L1 1
#define TCNT1L2 2
#define TCNT1L3 3
#define TCNT1L4 4
#define TCNT1L5 5
#define TCNT1L6 6
#define TCNT1L7 7
#define TCNT1H _SFR_MEM8(0x85)
#define TCNT1H0 0
#define TCNT1H1 1
#define TCNT1H2 2
#define TCNT1H3 3
#define TCNT1H4 4
#define TCNT1H5 5
#define TCNT1H6 6
#define TCNT1H7 7
#define ICR1 _SFR_MEM16(0x86)
#define ICR1L _SFR_MEM8(0x86)
#define ICR1L0 0
#define ICR1L1 1
#define ICR1L2 2
#define ICR1L3 3
#define ICR1L4 4
#define ICR1L5 5
#define ICR1L6 6
#define ICR1L7 7
#define ICR1H _SFR_MEM8(0x87)
#define ICR1H0 0
#define ICR1H1 1
#define ICR1H2 2
#define ICR1H3 3
#define ICR1H4 4
#define ICR1H5 5
#define ICR1H6 6
#define ICR1H7 7
#define OCR1A _SFR_MEM16(0x88)
#define OCR1AL _SFR_MEM8(0x88)
#define OCR1AL0 0
#define OCR1AL1 1
#define OCR1AL2 2
#define OCR1AL3 3
#define OCR1AL4 4
#define OCR1AL5 5
#define OCR1AL6 6
#define OCR1AL7 7
#define OCR1AH _SFR_MEM8(0x89)
#define OCR1AH0 0
#define OCR1AH1 1
#define OCR1AH2 2
#define OCR1AH3 3
#define OCR1AH4 4
#define OCR1AH5 5
#define OCR1AH6 6
#define OCR1AH7 7
#define OCR1B _SFR_MEM16(0x8A)
#define OCR1BL _SFR_MEM8(0x8A)
#define OCR1BL0 0
#define OCR1BL1 1
#define OCR1BL2 2
#define OCR1BL3 3
#define OCR1BL4 4
#define OCR1BL5 5
#define OCR1BL6 6
#define OCR1BL7 7
#define OCR1BH _SFR_MEM8(0x8B)
#define OCR1BH0 0
#define OCR1BH1 1
#define OCR1BH2 2
#define OCR1BH3 3
#define OCR1BH4 4
#define OCR1BH5 5
#define OCR1BH6 6
#define OCR1BH7 7
#define TCCR3A _SFR_MEM8(0x90)
#define WGM30 0
#define WGM31 1
#define COM3B0 4
#define COM3B1 5
#define COM3A0 6
#define COM3A1 7
#define TCCR3B _SFR_MEM8(0x91)
#define CS30 0
#define CS31 1
#define CS32 2
#define WGM32 3
#define WGM33 4
#define ICES3 6
#define ICNC3 7
#define TCCR3C _SFR_MEM8(0x92)
#define FOC3B 6
#define FOC3A 7
#define TCNT3 _SFR_MEM16(0x94)
#define TCNT3L _SFR_MEM8(0x94)
#define TCNT3L0 0
#define TCNT3L1 1
#define TCNT3L2 2
#define TCNT3L3 3
#define TCNT3L4 4
#define TCNT3L5 5
#define TCNT3L6 6
#define TCNT3L7 7
#define TCNT3H _SFR_MEM8(0x95)
#define TCNT3H0 0
#define TCNT3H1 1
#define TCNT3H2 2
#define TCNT3H3 3
#define TCNT3H4 4
#define TCNT3H5 5
#define TCNT3H6 6
#define TCNT3H7 7
#define ICR3 _SFR_MEM16(0x96)
#define ICR3L _SFR_MEM8(0x96)
#define ICR3L0 0
#define ICR3L1 1
#define ICR3L2 2
#define ICR3L3 3
#define ICR3L4 4
#define ICR3L5 5
#define ICR3L6 6
#define ICR3L7 7
#define ICR3H _SFR_MEM8(0x97)
#define ICR3H0 0
#define ICR3H1 1
#define ICR3H2 2
#define ICR3H3 3
#define ICR3H4 4
#define ICR3H5 5
#define ICR3H6 6
#define ICR3H7 7
#define OCR3A _SFR_MEM16(0x98)
#define OCR3AL _SFR_MEM8(0x98)
#define OCR3AL0 0
#define OCR3AL1 1
#define OCR3AL2 2
#define OCR3AL3 3
#define OCR3AL4 4
#define OCR3AL5 5
#define OCR3AL6 6
#define OCR3AL7 7
#define OCR3AH _SFR_MEM8(0x99)
#define OCR3AH0 0
#define OCR3AH1 1
#define OCR3AH2 2
#define OCR3AH3 3
#define OCR3AH4 4
#define OCR3AH5 5
#define OCR3AH6 6
#define OCR3AH7 7
#define OCR3B _SFR_MEM16(0x9A)
#define OCR3BL _SFR_MEM8(0x9A)
#define OCR3BL0 0
#define OCR3BL1 1
#define OCR3BL2 2
#define OCR3BL3 3
#define OCR3BL4 4
#define OCR3BL5 5
#define OCR3BL6 6
#define OCR3BL7 7
#define OCR3BH _SFR_MEM8(0x9B)
#define OCR3BH0 0
#define OCR3BH1 1
#define OCR3BH2 2
#define OCR3BH3 3
#define OCR3BH4 4
#define OCR3BH5 5
#define OCR3BH6 6
#define OCR3BH7 7
#define TCCR4A _SFR_MEM8(0xA0)
#define WGM40 0
#define WGM41 1
#define COM4B0 4
#define COM4B1 5
#define COM4A0 6
#define COM4A1 7
#define TCCR4B _SFR_MEM8(0xA1)
#define CS40 0
#define CS41 1
#define CS42 2
#define WGM42 3
#define WGM43 4
#define ICES4 6
#define ICNC4 7
#define TCCR4C _SFR_MEM8(0xA2)
#define FOC4B 6
#define FOC4A 7
#define TCNT4 _SFR_MEM16(0xA4)
#define TCNT4L _SFR_MEM8(0xA4)
#define TCNT4L0 0
#define TCNT4L1 1
#define TCNT4L2 2
#define TCNT4L3 3
#define TCNT4L4 4
#define TCNT4L5 5
#define TCNT4L6 6
#define TCNT4L7 7
#define TCNT4H _SFR_MEM8(0xA5)
#define TCNT4H0 0
#define TCNT4H1 1
#define TCNT4H2 2
#define TCNT4H3 3
#define TCNT4H4 4
#define TCNT4H5 5
#define TCNT4H6 6
#define TCNT4H7 7
#define ICR4 _SFR_MEM16(0xA6)
#define ICR4L _SFR_MEM8(0xA6)
#define ICR4L0 0
#define ICR4L1 1
#define ICR4L2 2
#define ICR4L3 3
#define ICR4L4 4
#define ICR4L5 5
#define ICR4L6 6
#define ICR4L7 7
#define ICR4H _SFR_MEM8(0xA7)
#define ICR4H0 0
#define ICR4H1 1
#define ICR4H2 2
#define ICR4H3 3
#define ICR4H4 4
#define ICR4H5 5
#define ICR4H6 6
#define ICR4H7 7
#define OCR4A _SFR_MEM16(0xA8)
#define OCR4AL _SFR_MEM8(0xA8)
#define OCR4AL0 0
#define OCR4AL1 1
#define OCR4AL2 2
#define OCR4AL3 3
#define OCR4AL4 4
#define OCR4AL5 5
#define OCR4AL6 6
#define OCR4AL7 7
#define OCR4AH _SFR_MEM8(0x99)
#define OCR4AH0 0
#define OCR4AH1 1
#define OCR4AH2 2
#define OCR4AH3 3
#define OCR4AH4 4
#define OCR4AH5 5
#define OCR4AH6 6
#define OCR4AH7 7
#define OCR4B _SFR_MEM16(0xAA)
#define OCR4BL _SFR_MEM8(0xAA)
#define OCR4BL0 0
#define OCR4BL1 1
#define OCR4BL2 2
#define OCR4BL3 3
#define OCR4BL4 4
#define OCR4BL5 5
#define OCR4BL6 6
#define OCR4BL7 7
#define OCR4BH _SFR_MEM8(0xAB)
#define OCR4BH0 0
#define OCR4BH1 1
#define OCR4BH2 2
#define OCR4BH3 3
#define OCR4BH4 4
#define OCR4BH5 5
#define OCR4BH6 6
#define OCR4BH7 7
#define SPCR1 _SFR_IO8(0xAC)
#define SPR10 0
#define SPR11 1
#define CPHA1 2
#define CPOL1 3
#define MSTR1 4
#define DORD1 5
#define SPE1 6
#define SPIE1 7
#define SPSR1 _SFR_IO8(0xAD)
#define SPI12X 0
#define WCOL1 6
#define SPIF1 7
#define SPDR1 _SFR_IO8(0xAE)
#define SPDR10 0
#define SPDR11 1
#define SPDR12 2
#define SPDR13 3
#define SPDR14 4
#define SPDR15 5
#define SPDR16 6
#define SPDR17 7
#define TCCR2A _SFR_MEM8(0xB0)
#define WGM20 0
#define WGM21 1
#define COM2B0 4
#define COM2B1 5
#define COM2A0 6
#define COM2A1 7
#define TCCR2B _SFR_MEM8(0xB1)
#define CS20 0
#define CS21 1
#define CS22 2
#define WGM22 3
#define FOC2B 6
#define FOC2A 7
#define TCNT2 _SFR_MEM8(0xB2)
#define TCNT2_0 0
#define TCNT2_1 1
#define TCNT2_2 2
#define TCNT2_3 3
#define TCNT2_4 4
#define TCNT2_5 5
#define TCNT2_6 6
#define TCNT2_7 7
#define OCR2A _SFR_MEM8(0xB3)
#define OCR2_0 0
#define OCR2_1 1
#define OCR2_2 2
#define OCR2_3 3
#define OCR2_4 4
#define OCR2_5 5
#define OCR2_6 6
#define OCR2_7 7
#define OCR2B _SFR_MEM8(0xB4)
#define OCR2_0 0
#define OCR2_1 1
#define OCR2_2 2
#define OCR2_3 3
#define OCR2_4 4
#define OCR2_5 5
#define OCR2_6 6
#define OCR2_7 7
#define ASSR _SFR_MEM8(0xB6)
#define TCR2BUB 0
#define TCR2AUB 1
#define OCR2BUB 2
#define OCR2AUB 3
#define TCN2UB 4
#define AS2 5
#define EXCLK 6
#define TWBR0 _SFR_MEM8(0xB8)
#define TWBR00 0
#define TWBR01 1
#define TWBR02 2
#define TWBR03 3
#define TWBR04 4
#define TWBR05 5
#define TWBR06 6
#define TWBR07 7
#define TWSR0 _SFR_MEM8(0xB9)
#define TWPS00 0
#define TWPS01 1
#define TWS03 3
#define TWS04 4
#define TWS05 5
#define TWS06 6
#define TWS07 7
#define TWAR0 _SFR_MEM8(0xBA)
#define TWGCE0 0
#define TWA00 1
#define TWA01 2
#define TWA02 3
#define TWA03 4
#define TWA04 5
#define TWA05 6
#define TWA06 7
#define TWDR0 _SFR_MEM8(0xBB)
#define TWD00 0
#define TWD01 1
#define TWD02 2
#define TWD03 3
#define TWD04 4
#define TWD05 5
#define TWD06 6
#define TWD07 7
#define TWCR0 _SFR_MEM8(0xBC)
#define TWIE0 0
#define TWEN0 2
#define TWWC0 3
#define TWSTO0 4
#define TWSTA0 5
#define TWEA0 6
#define TWINT0 7
#define TWAMR0 _SFR_MEM8(0xBD)
#define TWAM00 0
#define TWAM01 1
#define TWAM02 2
#define TWAM03 3
#define TWAM04 4
#define TWAM05 5
#define TWAM06 6
#define UCSR0A _SFR_MEM8(0xC0)
#define MPCM0 0
#define U2X0 1
#define UPE0 2
#define DOR0 3
#define FE0 4
#define UDRE0 5
#define TXC0 6
#define RXC0 7
#define UCSR0B _SFR_MEM8(0xC1)
#define TXB80 0
#define RXB80 1
#define UCSZ02 2
#define TXEN0 3
#define RXEN0 4
#define UDRIE0 5
#define TXCIE0 6
#define RXCIE0 7
#define UCSR0C _SFR_MEM8(0xC2)
#define UCPOL0 0
#define UCSZ00 1
#define UCPHA0 1
#define UCSZ01 2
#define UDORD0 2
#define USBS0 3
#define UPM00 4
#define UPM01 5
#define UMSEL00 6
#define UMSEL01 7
#define UCSR0D _SFR_MEM8(0xC3)
#define SFDE0 5
#define RXS0 6
#define RXIE0 7
#define UBRR0 _SFR_MEM16(0xC4)
#define UBRR0L _SFR_MEM8(0xC4)
#define UBRR0_0 0
#define UBRR0_1 1
#define UBRR0_2 2
#define UBRR0_3 3
#define UBRR0_4 4
#define UBRR0_5 5
#define UBRR0_6 6
#define UBRR0_7 7
#define UBRR0H _SFR_MEM8(0xC5)
#define UBRR0_8 0
#define UBRR0_9 1
#define UBRR0_10 2
#define UBRR0_11 3
#define UDR0 _SFR_MEM8(0xC6)
#define UDR0_0 0
#define UDR0_1 1
#define UDR0_2 2
#define UDR0_3 3
#define UDR0_4 4
#define UDR0_5 5
#define UDR0_6 6
#define UDR0_7 7
#define UCSR1A _SFR_MEM8(0xC8)
#define MPCM1 0
#define U2X1 1
#define UPE1 2
#define DOR1 3
#define FE1 4
#define UDRE1 5
#define TXC1 6
#define RXC1 7
#define UCSR1B _SFR_MEM8(0xC9)
#define TXB81 0
#define RXB81 1
#define UCSZ12 2
#define TXEN1 3
#define RXEN1 4
#define UDRIE1 5
#define TXCIE1 6
#define RXCIE1 7
#define UCSR1C _SFR_MEM8(0xCA)
#define UCPOL1 0
#define UCSZ10 1
#define UCPHA1 1
#define UCSZ11 2
#define UDORD1 2
#define USBS1 3
#define UPM10 4
#define UPM11 5
#define UMSEL10 6
#define UMSEL11 7
#define UCSR1D _SFR_MEM8(0xCB)
#define SFDE1 5
#define RXS1 6
#define RXIE1 7
#define UBRR1 _SFR_MEM16(0xCC)
#define UBRR1L _SFR_MEM8(0xCC)
#define UBRR1_0 0
#define UBRR1_1 1
#define UBRR1_2 2
#define UBRR1_3 3
#define UBRR1_4 4
#define UBRR1_5 5
#define UBRR1_6 6
#define UBRR1_7 7
#define UBRR1H _SFR_MEM8(0xCD)
#define UBRR1_8 0
#define UBRR1_9 1
#define UBRR1_10 2
#define UBRR1_11 3
#define UDR1 _SFR_MEM8(0xCE)
#define UDR1_0 0
#define UDR1_1 1
#define UDR1_2 2
#define UDR1_3 3
#define UDR1_4 4
#define UDR1_5 5
#define UDR1_6 6
#define UDR1_7 7
#define TWBR1 _SFR_MEM8(0xD8)
#define TWBR10 0
#define TWBR11 1
#define TWBR12 2
#define TWBR13 3
#define TWBR14 4
#define TWBR15 5
#define TWBR16 6
#define TWBR17 7
#define TWSR1 _SFR_MEM8(0xD9)
#define TWPS10 0
#define TWPS11 1
#define TWS13 3
#define TWS14 4
#define TWS15 5
#define TWS16 6
#define TWS17 7
#define TWAR1 _SFR_MEM8(0xDA)
#define TWGCE1 0
#define TWA10 1
#define TWA11 2
#define TWA12 3
#define TWA13 4
#define TWA14 5
#define TWA15 6
#define TWA16 7
#define TWDR1 _SFR_MEM8(0xDB)
#define TWD10 0
#define TWD11 1
#define TWD12 2
#define TWD13 3
#define TWD14 4
#define TWD15 5
#define TWD16 6
#define TWD17 7
#define TWCR1 _SFR_MEM8(0xDC)
#define TWIE1 0
#define TWEN1 2
#define TWWC1 3
#define TWSTO1 4
#define TWSTA1 5
#define TWEA1 6
#define TWINT1 7
#define TWAMR1 _SFR_MEM8(0xDD)
#define TWAM10 0
#define TWAM11 1
#define TWAM12 2
#define TWAM13 3
#define TWAM14 4
#define TWAM15 5
#define TWAM16 6
/* Interrupt Vectors */
/* Interrupt Vector 0 is the reset vector. */
#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */
#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */
#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */
#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */
#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */
#define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */
#define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */
#define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */
#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */
#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */
#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */
#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */
#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */
#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */
#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */
#define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */
#define SPI0_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */
#define USART0_RX_vect _VECTOR(18) /* USART Rx Complete */
#define USART0_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */
#define USART0_TX_vect _VECTOR(20) /* USART Tx Complete */
#define ADC_vect _VECTOR(21) /* ADC Conversion Complete */
#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */
#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */
#define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */
#define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */
#define USART0_START_vect _VECTOR(26) /*USART0 Start frame detection*/
#define PCINT3_vect _VECTOR(27) /*Pin Change Interrupt Request 3*/
#define USART1_RX_vect _VECTOR(28) /*USART0 Rx Complete*/
#define USART1_UDRE_vect _VECTOR(29) /*USART0, Data Register Empty*/
#define USART1_TX_vect _VECTOR(30) /*USART0, Tx Complete*/
#define USART1_START_vect _VECTOR(31) /*USART1 Start frame detection*/
#define TIMER3_CAPT_vect _VECTOR(32) /*Timer/Counter3 Capture Event*/
#define TIMER3_COMPA_vect _VECTOR(33) /*Timer/Counter3 Compare Match A*/
#define TIMER3_COMPB_vect _VECTOR(34) /*Timer/Coutner3 Compare Match B*/
#define TIMER3_OVF_vect _VECTOR(35) /*Timer/Counter3 Overflow*/
#define CFD_vect _VECTOR(36) /*Clock failure detection interrrupt*/
#define PTC_EOC_vect _VECTOR(37) /*PTC End of Conversion*/
#define PTC_WCOMP_vect _VECTOR(38) /*PTC Window comparator mode*/
#define SPI1_STC_vect _VECTOR(39) /*SPI1 Serial Transfer Complete*/
#define TWI1 TWI1_vect _VECTOR(40) /*Transfer complete*/
#define TIMER4_CAPT_vect _VECTOR(41) /*Timer/Counter4 Capture Event*/
#define TIMER4_COMPA_vect _VECTOR(42) /*Timer/Counter4 Compare Match A*/
#define TIMER4_COMPB_vect _VECTOR(43) /*Timer/Coutner4 Compare Match B*/
#define TIMER4_OVF_vect _VECTOR(44) /*Timer/Counter4 Overflow*/
#define _VECTORS_SIZE (45 * 4)
/* Constants */
#define SPM_PAGESIZE 128
#define RAMEND 0x8FF /* Last On-Chip SRAM Location */
#define XRAMSIZE 0
#define XRAMEND RAMEND
#define E2END 0x3FF
#define E2PAGESIZE 4
#define FLASHEND 0x7FFF
/* Fuses */
#define FUSE_MEMORY_SIZE 3
/* Low Fuse Byte */
#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */
#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */
#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */
#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
/* High Fuse Byte */
#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */
#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */
#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */
#define HFUSE_DEFAULT (FUSE_SPIEN)
/* Extended Fuse Byte */
#define FUSE_BOOTRST (unsigned char)~_BV(0)
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
/* Signature */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x95
#define SIGNATURE_2 0x16
#endif /* _AVR_IOM328PB_H_ */
Diese Datei wurde aus der ursprünglichen iom328p.h entwickelt.
Die Fuses und Lock Bits hab ich noch nicht bearbeitet.
Im Datenblatt von ATMEL für den 328pb sind auch noch so einige Bezeichnungsfehler drin.
Da der Controller im Studio 4 leider nicht simuliert werden kann, werd ich da ne andere Lösung finden müssen.